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L50-501 LSI SVM5 Implementation Engineer

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L50-501 exam Dumps Source : LSI SVM5 Implementation Engineer

Test Code : L50-501
Test denomination : LSI SVM5 Implementation Engineer
Vendor denomination : LSI
braindumps : 119 existent Questions

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LSI LSI SVM5 Implementation Engineer

LSI Industries: Planning For A shiny Future | killexams.com existent Questions and Pass4sure dumps

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NFPA 110: ordinary for Emergency and Standby energy systems prolonged braindumps | killexams.com existent Questions and Pass4sure dumps

contemporary Consulting-Specifying Engineer webcast presenters Tom Divine, PE, project supervisor, Smith Seckman Reid Inc., and Kenneth Kutsmeda, PE, LEED AP, Jacobs Engineering, reply reader questions on what newfangled code necessities will imply for consulting engineers.

Tom Divine, PE, Project Manager, Smith Seckman Reid Inc., and Kenneth Kutsmeda, PE, LEED AP, Jacobs EngineeringQ: When is it required to prize a 3 pole and four pole ATS?

  • Tom Divine: When the generator is a one after the other-derived device, a 4-pole ATS is required for circuits with a neutral.  If the circuit has no neutral, a three-pole ATS will suffice.  The goal of the requirement is to avoid multiple connections between neutral and ground, which may deliver alternate paths for neutral latest, and intuition wrong operation of ground fault protection for gadget.
  • Q: With recognize to breaker coordination; what are the favorite electronic trips: LI, LS/I, LSI, or LSIG?

  • Kenneth Kutsmeda: LSI or LSIG are favorite as a result of they provide essentially the most flexibility when trying to coordinate.  in case you try to serve Article seven hundred- or Article 708-class loads, pay cautious attention to the selective coordination requirement when determining strain back and forth instruments.
  • Q: enact you advocate dual hot-standby manage PLCs when installing parallel gensets?

  • Kutsmeda: yes, if the undertaking can prize the funds for the further cost, i'd recommend twin control PLCs.  This prevents the PLC from fitting a single ingredient of failure.
  • Q: Are schools regarded to exist stage 1 or degree 2 amenities? usually, stage 1 is needed for fitness supervision or mission captious facilities handiest.

  • Divine: “degree 1” describes a paraphernalia whose failure might result in loss of life or ascetic injury to a person.  That could succeed to a mission essential facility, or may not.  It actually applies to any facility that gives vital care.  Intuitively, I’d forecast a faculty to exist a degree 2 facility, since it doesn’t provide services whose sudden failure would depart someone exposed to injury.  I’d imply getting the view of complete the AHJ’s before proceeding with a design, although.  It’s now not inconceivable to accomplish a case that the failure of an emergency gadget complete the passage through an evacuation event could exist catastrophic, and an AHJ could Take the view that it’s stage 1.
  • Q: what's the intent/aim of somatic isolating the primary department and lifestyles defense branches? Can one prize a uncertain repercussion on the different?

  • Kutsmeda: The separation is mostly to present protection to against damage and/or a cable fireplace. You enact not desire a cable fire on a widely wide-spread circuit taking out a captious circuit.
  • Q: Is mineral-insulated (MI) cable obligatory for not obligatory standby generator feeder circuits?

  • Divine: MI cable isn’t required with the aid of the NFPA codes.  It’s probably the most methods of complying with requirements for fireplace ranking of emergency feeders in NEC 700.9.  It’s my figuring out that some jurisdictions require it for unavoidable functions, however that requirement doesn’t near up from NFPA ninety nine or NFPA 110, or from the NEC.
  • Q: Does the ten-2nd vigour restoration start time apply to the main service or to the conclusion expend gadget?

  • Kutsmeda: The NEC states the latest deliver to emergency lights and power shall exist attainable with time required for the application but now not to exceed 10 seconds.  In my adventure the AHJ has interpreted that to imply energy/existing available at the quit expend equipment.
  • Q: Does the emergency device consist of conductors and different device upstream from an ATS on the regular aspect of the ATS?

  • Kutsmeda: No, the emergency system doesn't comprehend machine or feeders upstream from the ATS on the ordinary aspect.
  • Q: should the emergency provider switchboard that feeds the ATSs exist in a divide elbowroom from the elbowroom that contains the ATSs?

  • Divine: It doesn’t requisite to be.  NFPA 110 requires that the EPS, which might consist of generators and paralleling gear, to exist attach in in a divide elbowroom for level-1 techniques.  nevertheless it peculiarly allows for EPSS device and transfer switches, to exist installed in that room.
  • Q: If the only vital concern is egress lights, can that exist addressed with battery lights, and if so, can my system exist standby best?

  • Kutsmeda: yes, the paraphernalia can exist standby rated if the lights is addressed by means of individual batteries or a primary inverter equipment.  here's quite typical with paralleled systems that may’t meet the 10 2d requirement.
  • Q: When referring to the NEC as regarding the EPSS, enact you deserve to additionally harmonize with article 695 elevators and 517 hospitals for further requirements?

  • Kutsmeda: sure, there are specific necessities in each of those sections for EPSS-classification systems.
  • Q: How lengthy does the crank examine should exist accomplished on the generator?

  • Divine: That requirement seems in 7.13.4.four.2 in both the 2010 and 2013 variations of NFPA 110.  They reference the crank and rest cycles described in 5.6.four.2, which calls for 15 seconds of cranking, adopted through 15 seconds of rest, repeated three times.
  • Q: Is the expend of closed transition transfer switches informed for level 1 facilities? Any concerns with the usage of closed transition switches?

  • Kutsmeda: Closed transition isn't a requirement.  it is recommended for those methods that don't requisite to Take yet another outage transferring returned to utility.  for example, vigour methods that serve life succor or surgical procedure class gadget may additionally wish to accept as suitable with closed transition.  Many mission captious ilk facilities expend closed transition to avert the mechanical systems from shutting down complete the passage through the switch again to utility (vigor backup through UPS).  Closed transition switches deserve to prize some class of synch check to steer pellucid of closing two sources out of fraction and protection to avert again-feeding the utility.
  • Q: What are the requirements for the life security and significant branch programs when the constructing—specifically a talented nursing facility—has a complete structure backup generator? enact you silent require divide ATSs, besides the fact that they prize divide panels and wiring within the constructing? Contractors reckon here's now not essential.

  • Divine: Articles 517.40 through 517.forty four picture necessities for “nursing homes and restricted supervision amenities.”  Article 517.forty one(B) requires a divide transfer change for every department, unless the total load is under one hundred fifty kVA.  There’s no exception for a complete structure backup, and there are requirements for load to exist staged onto the equipment.
  • Q: If I even prize a device per Article 701 and Article 702 software, what branches enact the battery charger, gasoline pump, and dampers obtain connected to?

  • Kutsmeda: Article 701.  The device required to office the generator will exist connected to the highest level for which that generator serves.
  • Q: If a sanatorium is to exist 100% backed up with the aid of turbines, is it a violation of NEC 517.30(B)(4)-switch Switches to obtain rid of complete switch switches by using providing Medium Voltage generators and tie them thru a paralleling paraphernalia to a Medium Voltage Distribution Switchgear at the significant Utility Plant? switch of vigour may exist at the Medium Voltage switchgear.

  • Divine: Presuming a load of more than 150 kVA, this scheme doesn’t meet the black-letter requirements of 517.30(B)(four), which requires divide switch switches for the emergency branches and the paraphernalia gadget.  I don’t note that the rest in the gadget can organize for delayed connection of the machine gadget, as required in 517.34.  at last, this scheme will dash afoul of NFPA 110 6.1.6, 2013 version, which requires transfer switches to exist listed assemblies where accessible, and makes it viable for medium-voltage transfer by the expend of interlocked circuit breakers for less than mechanical and crucial plant hundreds. 
  • Q: might the 517.34 paraphernalia exist considered as a 701 device?

  • Kutsmeda: sure, the hundreds recognized in Article 517.34 fraction (A) may exist considered as a 701 device.  masses identified in 517.34 section (B) could exist considered as a 702 system as a result of they are not required to exist automatic.
  • Q: To verify under on-website or transportable load monetary institution, enact amenities prize a checking out switch change to connect the weight monetary institution to the gadget and supply that auto removal of load monetary institution if utility energy fails birthright through load monetary institution testing?

  • Divine: I’ve not ever considered that implementation.  The basic feature of a switch swap is to maintain load energized.  There’s nothing particular about a transfer switch as a system of de-energizing whatever thing dote a load bank.  customarily, I’ve considered a committed breaker within the generator distribution switchgear for that purpose, or every so often an outside disconnect change connected to any such breaker.  The requirement is that equal masses—the tribulation monetary institution—get replaced with emergency masses—the power’s load—if the basic supply fails.  That could exist carried out with a control relay that journeys the load bank if typical vim fails, or it might exist done through connecting the emergency load as a fraction of the examine, and supplementing with a load bank.
  • Q: are you able to combine Article seven hundred-class masses and Article 701-classification loads in the equal switchgear and on the identical OCPD of a generator?

  • Kutsmeda: which you can combine seven hundred and 701 class masses on the identical switchgear with a touchstone OCPD on the output of the generator.  The seven hundred and 701 loads should exist on divide feeders with divide OCPD on each feeder and the OCPD for the seven-hundred ilk hundreds requisite to exist determined in divide vertical sections of the switchgear.
  • Q: whereas performing the two hour load verify per 7.13.four.3, I assume the generator OEM manufacturing facility can accomplish only a 2 hour reactive load verify at rated power factor to harmonize to 7.13.4.three.2, relevant?

  • Divine: NFPA 7.13.four.3.2 says that the acceptance verify will besides exist carried out at harmony energy aspect the expend of a strictly resistive load monetary institution if the manufacturer has tested the mills at rated load and rated vigour ingredient.  
  • – Edited by using Jessica DuBois-Maahs, affiliate content supervisor, CFE Media, jdmaahs(a)cfemedia.com.

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    A Design Methodology for constructing method-unbiased Hardmacro IP | killexams.com existent Questions and Pass4sure dumps

    swiftly migrating highbrow property (IP) from one foundry to yet another and from one technique node to the next will besides exist a difficult, however indispensable, a fraction of the business, mainly if the IP is generated and delivered as hardmacro IP.  That’s as a result of tough IP or a GDSII netlist versus soft IP, RTL or gate-stage netlist ought to exist accessible for complete primary foundries and for a great altenative of technique nodes at each foundry.

    Designing newfangled reminiscence IP is essentially a manual assignment that includes greater analog circuits —cost pumps, voltage regulators and suffer amplifiers, for illustration — than most common sense designs.  At four megabytes (Mb), the design tribulation dealing with the layout supervisor and his implementation crew is bold. 

    These considerations are universal of reminiscence design, and the Kilopass team ran into them when designing a coincident 4-Mb reminiscence IP block.  Its suffer offers techniques through which other groups can overcome these challenges.

    To ease the burden, the group recognized facets of the design that could exist automated, liberating them to pay attention to essential analog elements that ought to exist tailor-made for someone foundry and technique.  The outcome is an electronic design automation (EDA) device strain developed for the newest anti-fuse non-unstable reminiscence (NVM) product line. 

    Exploiting the EDA device circulation

    the expend of commercially purchasable EDA solutions, the primary task to exist automated was speedy and accurate entry of design concepts, together with managing design intent in a system that flowed naturally in the schematic.  This allowed designers to visualize and Take into account the numerous interdependencies of an analog or mixed-signal design and its results on circuit performance.

    In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by using an additional inside team.  The project of merging the current layout with the rest of the reminiscence design became a simple system requiring a day of manual vicinity and route or connecting I/Os and routing vim and floor. 

    The crew made expend of the potential to embed design constraints within the netlist handed between the entrance-end design team and the implementation team.  Up unless that point, those constraints had been communicated by using cryptic notes on the schematic.  as an example:  Specify that two gates obligatory to exist matched or a particular internet is captious and its optimum size requisite to no longer exist passed within the layout.  Communicated the ancient manner, when the schematic become given to the implementation engineer, the designer could simplest hope that the implementation crew achieved the favored effect. 

    Managing Complexity

    The implementation crew built a brand newfangled reminiscence with the aid of making a single reminiscence mobile then replicated it to build the more complicated arrays — a bottom-up approach versus the universal right-down approach that tremendous digital SoC design groups accomplish expend of.  The reminiscence consisted of by a long shot cell comprising two transistors.  

    once the bit mobilephone was created and optimized, the telephone became replicated along a horizontal line of size n (32, for instance), as several in the schematic.  once the line of reminiscence cells became created, it turned into replicated vertically m number of rows (32, as an example), as targeted in the schematic.  during this method, the implementation engineer created a 1-Mb reminiscence array.  The system was repeated three more instances to create the 4-Mb memory, a two-via-two matrix of 1-Mb arrays.

    In setting up the preparatory netlist, the front-end dressmaker labeled each of the bit cells and its linked vigor, ground, bit line and note line.  He then precise the number of bit cells to exist powered by passage of a given energy internet to accomplish unavoidable that each phone obtained the equal quantity of present.

    The capacity to set constraints in the netlist passed to the implementation engineer ensured the design intent became captured in closing layout. 

    Automating Repetitive sheperd projects

    Automating repetitive projects tremendously decreased the time to complete the layout as neatly.  for example, labeling the bit line, notice line, feel amplifier, and energy and ground for a 4-Mb reminiscence can Take appreciable time if done manually.  Surrendering the assignment to the EDA device reduced the chore to a handful of keyboard operations.

    In a pull-down menu, the implementation engineer achieved a configuration that asked for the signal identify, variety of pins to exist labeled, x and y coordinates of the first signal, spacing between pins, and the measurement of the text.  From this counsel, the design device created each particular person signal name.

    once the reminiscence IP become applied for the 40-nanometer (nm) technique at foundry A, the layout crew turned into confronted with converting the reminiscence to 40 nm at one other foundry.  With the automated EDA stream, this was decreased to a two-step procedure:  layer mapping followed by statistics manipulation.  in the first step, the mapping table for foundry A’s forty-nm library become changed with the mapping desk for foundry B’s 40-nm library.  The appliance then immediately produced a layout for foundry B.  The system became not absolutely automatic, as every foundry has its own exciting rules; hence exceptions that don't map one-to-one are highlighted.

    The implementation engineer examined complete generated exceptions then made fundamental alterations.  as an instance, in foundry A, the bit phone might besides expend layer C and D, whereas in foundry B, layer D and E are used.  once the conversion changed into accomplished, a design rule examine (DRC) become performed along with remaining verification. 

    This automation took half the time compared with ranging from scratch, enabling rapid migration of IP from one foundry to an additional.  while designing newfangled reminiscence IP, such as Kilopass’ Gusto anti-fuse NVM, continues to exist more often than not a sheperd effort, facets may besides exist automated, enabling the layout and implementation group to concentrate on captious analog features that must exist tailor-made for a person foundry and process.  

    creator Bio:  Bernd Stamme is Director for advertising and functions at Kilopass know-how.  He has more than 15 years of suffer within the IP and semiconductor industry. prior to Kilopass, he become the Director of IP know-how at SiRF technology managing the licensing and a success integration of third-celebration IP into SiRF’s GPS chip units.  earlier than SiRF, he held administration positions in LSI logic’s CoreWare organization and worked on high-pace SerDes IP, communication interfaces and processor core.  Stamme holds a Dipl.-Ing. degree in Electrical Engineering from FH Bielefeld in Germany.


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    LSI SVM5 Implementation Engineer

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    A Design Methodology for structure Process-Independent Hardmacro IP | killexams.com existent questions and Pass4sure dumps

    Rapidly migrating intellectual property (IP) from one foundry to another and from one process node to the next can exist a challenging, but necessary, fraction of the business, especially if the IP is generated and delivered as hardmacro IP.  That’s because difficult IP or a GDSII netlist versus soft IP, RTL or gate-level netlist must exist available for complete major foundries and for a wide selection of process nodes at each foundry.

    Designing newfangled reminiscence IP is largely a manual task that involves more analog circuits —charge pumps, voltage regulators and sense amplifiers, for illustration — than most logic designs.  At four megabytes (Mb), the design tribulation facing the layout manager and his implementation team is formidable. 

    These issues are typical of reminiscence design, and the Kilopass team ran into them when designing a recent 4-Mb reminiscence IP block.  Its suffer offers ways in which other teams can overcome these challenges.

    To ease the burden, the team identified elements of the design that could exist automated, freeing them to concentrate on captious analog elements that must exist tailored for an individual foundry and process.  The result is an electronic design automation (EDA) appliance flux developed for the latest anti-fuse non-volatile reminiscence (NVM) product line. 

    Exploiting the EDA appliance Flow

    Using commercially available EDA solutions, the first task to exist automated was rapid and accurate entry of design concepts, including managing design intent in a passage that flowed naturally in the schematic.  This allowed designers to visualize and understand the many interdependencies of an analog or mixed-signal design and its effects on circuit performance.

    In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by another internal team.  The task of merging the existing layout with the rest of the reminiscence design was a simple process requiring a day of manual situation and route or connecting I/Os and routing power and ground. 

    The team made expend of the talent to embed design constraints in the netlist passed between the front-end design team and the implementation team.  Up until that point, those constraints were communicated by cryptic notes on the schematic.  For example:  Specify that two gates needed to exist matched or a specific net is captious and its maximum length must not exist exceeded in the layout.  Communicated the ragged way, when the schematic was given to the implementation engineer, the designer could only hope that the implementation team achieved the desired result. 

    Managing Complexity

    The implementation team built a newfangled reminiscence by creating a single reminiscence cell then replicated it to build the more knotty arrays — a bottom-up approach versus the conventional top-down approach that great digital SoC design teams employ.  The reminiscence consisted of a bit cell comprising two transistors.  

    Once the bit cell was created and optimized, the cell was replicated along a horizontal line of length n (32, for example), as specified in the schematic.  Once the line of reminiscence cells was created, it was replicated vertically m number of rows (32, for example), as specified in the schematic.  In this manner, the implementation engineer created a 1-Mb reminiscence array.  The process was repeated three more times to create the 4-Mb memory, a two-by-two matrix of 1-Mb arrays.

    In developing the initial netlist, the front-end designer labeled each of the bit cells and its associated power, ground, bit line and word line.  He then specified the number of bit cells to exist powered by a given power net to ensure that each cell received the identical amount of current.

    The talent to set constraints in the netlist passed to the implementation engineer ensured the design intent was captured in final layout. 

    Automating Repetitive Manual Tasks

    Automating repetitive tasks greatly reduced the time to complete the layout as well.  For example, labeling the bit line, word line, sense amplifier, and power and ground for a 4-Mb reminiscence can Take considerable time if done manually.  Surrendering the task to the EDA appliance reduced the chore to a handful of keyboard operations.

    In a pull-down menu, the implementation engineer completed a configuration that asked for the signal name, number of pins to exist labeled, x and y coordinates of the first signal, spacing between pins, and the size of the text.  From this information, the design appliance created each individual signal name.

    Once the reminiscence IP was implemented for the 40-nanometer (nm) process at foundry A, the layout team was confronted with converting the reminiscence to 40 nm at another foundry.  With the automated EDA flow, this was reduced to a two-step process:  layer mapping followed by data manipulation.  In the first step, the mapping table for foundry A’s 40-nm library was replaced with the mapping table for foundry B’s 40-nm library.  The appliance then automatically produced a layout for foundry B.  The process was not completely automated, as each foundry has its own unique rules; thus exceptions that enact not map one-to-one are highlighted.

    The implementation engineer examined complete generated exceptions then made necessary adjustments.  For example, in foundry A, the bit cell may expend layer C and D, whereas in foundry B, layer D and E are used.  Once the conversion was completed, a design rule check (DRC) was performed along with final verification. 

    This automation took half the time compared with starting from scratch, enabling rapid migration of IP from one foundry to another.  While designing newfangled reminiscence IP, such as Kilopass’ Gusto anti-fuse NVM, continues to exist mostly a manual effort, elements can exist automated, enabling the layout and implementation team to concentrate on captious analog elements that must exist tailored for an individual foundry and process.  

    Author Bio:  Bernd Stamme is Director for Marketing and Applications at Kilopass Technology.  He has more than 15 years of suffer in the IP and semiconductor industry. Prior to Kilopass, he was the Director of IP Technology at SiRF Technology managing the licensing and successful integration of third-party IP into SiRF’s GPS chip sets.  Before SiRF, he held management positions in LSI Logic’s CoreWare organization and worked on high-speed SerDes IP, communication interfaces and processor core.  Stamme holds a Dipl.-Ing. Degree in Electrical Engineering from FH Bielefeld in Germany.


    LSI Industries: Planning For A lustrous Future | killexams.com existent questions and Pass4sure dumps

    No result found, try newfangled keyword!LSI Industries' participate price has declined significantly in the ... They should note, in addition, that the author of this article is himself a licensed professional architectural engineer who has specifi...

    Video Encoding: strain for the Specialist or the Jack-of-All-Trades? | killexams.com existent questions and Pass4sure dumps

    One of the hardest choices encoding technicians prize to accomplish is deciding between hardware and software. Hardware-based encoders and transcoders prize had a performance advantage over software since computers were invented. That's because dedicated, limited-purpose processors are designed to dash a specific algorithm, while the general-purpose processor that runs encoding software is designed to exploit several functions. It's the specialist versus the jack-of-all-trades.

    In the past few years, processors and workflows prize changed. The considerable disruptor has been time and the economics of Moore's Law, which famously says that the number of transistors incorporated in a chip will approximately double every 24 months. The analytic outcome of Moore's law is that the CPUs obtain more powerful by a factor of two every few years, but more recently processing power seems to double every few months. Lately, Intel -- whose co-founder Gordon Moore coined Moore's Law -- has been adding specialty functions along with its math co-processors to equalize the differences between general-use processors and specialty processors.

    There are many layers and elements to both a general-purpose processor and a task-specific hardware processor. The general-purpose CPU is the most common -- there are literally billions of them in complete manner of computing devices -- while the more purpose-oriented processors comprehend digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and integrated circuits (ICs) that are available for various industrial appliances and widely used in cellphones. Many of the structures and elements are similar across complete types, but there are considerable differences. If you are not intimate with the elements of the various types, here are the basic structures of both.

    The General-Purpose CPU

    The general-purpose CPU is laid out with resilient core elements as the arithmetic logic unit (ALU), control unit (CU), and accessory elements that present extra features for performance. Basically these two cores talk to each other, bring in reminiscence as needed, and transmit labor to the other elements. Other elements comprehend I/O processors, logic gates, integrated circuits, and -- on most newer processors and especially on the Intel Xeon processors -- a beefy math co-processor. The math co-processor assists the ALU and can exploit the more extreme and knotty mathematical computations. Essentially, it gives the processor the extra horsepower it might require.

    The Dedicated Processor

    Specific-purpose hardware encoders prize been around longer than general-purpose processors, and the latter prize been slower at mathematical equations or algorithm problems. History is vitally primary to understand the market and technology, not to mention obtain a sense of what the future holds. The earliest illustration of encoding was in 1965, when the Intelsat 1 (Early Bird) became the first commercial deployment of a satellite to downlink video and audio. Since then, the world has been using specific processors to process video, and the technology has made leaps and bounds to present higher density and quality.

    Video ARM DSP

    This is a universal layout of a video ARM DSP. The ARM core runs the embedded operating system, working dote a traffic cop to control input and output. 

    Dedicated processors -- such as dedicated signal processors (DSPs), graphics processing units (GPUs), and vector processors -- complete prize a very similar design structure. A basic and most common ingredient is an I/O manager, which has a tiny onboard operating system along with memory. This is the traffic cop, controlling input and output. Then there are multiple specialized processing modules that execute the desired instructions very quickly and that DSPs and other dedicated processors support. Unlike a general-purpose processor, which has many viable universal instructions that may not exist most efficient for the task at hand, dedicated processors confidence on accelerated, per-function instructions that are more job-specific.

    Dedicated processors and encoders prize a variety of applications and workflows. If you gape at the major users of professional encoders, you will note that in many cases they confidence on specialized encoders. The following well-known companies accomplish DSP chips: LSI Corp.; Texas Instruments, Inc.; Analog Devices, Inc.; Sony; and Magnum Semiconductor. These DSPs are used in devices such as media gateways, telepresence devices, cellphones, and military and radar processing.

    FPGAs are now very approved implementations of DSP functions because of their flexibility of setup and upgrade. Since they are field-upgradeable, their development costs for the user are significantly cheaper than DSPs and application-specific integrated circuits (ASICs; more on those in a moment) from the traditional DSP providers. You can note FGPAs from Altera Corp. and Xilinx, Inc. that prize DSP functions built in. If you want a board or system that is easier to upgrade in the field, then this is probably the best passage to go.

    DSP Packets

    While each manufacturer will tweak its design slightly, this is an overview of how communications and packets flux into the modules of DSPs and ASICs. 

    Another implementation of the dedicated processor is the ASIC. These factory-programmed DSPs are used everywhere cost is a crucial consideration, because they present special functionality at optimal price and performance. In general, they are more expensive to design but are cost-effective for any appliance or board manufacturer to implement into their systems. Many manufacturers of DSPs besides manufacture ASICs; companies such as NXP Semiconductors, Broadcom Corp., and Freescale, Inc. besides accomplish custom ASIC DSPs.

    If you ever open up a hardware encoding appliance -- from IP media gateways to broadcast encoder and decoders -- you will note several of the chips previously listed. You can find appliances for every industry. Today you will find a dedicated hardware-based encoding device from Harmonic, Inc.; Harris; Tandberg Data; or NTT Communications in every TV station or cable TV headend, and you'll find appliances or cards from ViewCast Corp. or Digital Rapids in many hybrid encoding farms, since they accelerate some of the functions in the hardware. If you've watched a video on YouTube, then you prize seen video encoded by RGB Networks with the RipCode equipment, which used massive numbers of Texas Instruments, Inc. DSPs.

    Pros and Cons of Hardware Encoders

    There are always some pros and cons when it comes to specific design hardware encoders and dedicated appliances. The dedicated hardware approach with DSPs or chips is the impeccable solution for media gateways and in low latency military applications. They are designed to dash 24/7 with puny or no human interaction. There are some processors that can encode an entire frame in the 1ms-10ms (millisecond) purview and FPGAs that can encode in the 10ms-30ms range. These processes allow for the creation of appliances where the encoding latency is less than 100ms from encode to transmission to decode. birthright now you can only obtain low latency using the birthright DSPs, ASICs, and FPGAs. The tolerable lifespan of an appliance is 5-10 years depending on the configuration and manufacturer. Similar lifetimes are assumed for systems that rarely change, such as satellite uplink or cable system encoders.

    The primary drawback of dedicated hardware-based encoding is that the codec on the processor is generally impossible to upgrade. Every DSP, ASIC, or FPGA is based on an algorithm that was finalized years ago. By the time the chip is ready to exist sold, the codec is 6 months to a year old. Add more design cycles for the appliance development and manufacturing, and the quit result is a device based on a codec that's a year or more old. If improvement to the codec comes out, the chip or device might never exist able to integrate the newfangled codec or technology due to the manufacturer or the passage the chip was designed. The dedicated DSP approach can reclaim a lot of money, but at the expense of flexibility. Those chips enact just what they were originally designed to enact and nothing more.

    Hardware Encoder

    Video comes into a hardware encoder to a media gateway, which will accomplish adjustments to the video stream to address network conditions and the quit user’s video decoding device. When done, it will transmit these modifications to the video decoder. 

    There's another issue with dedicated chip-based encoders: Who determines the trait of the codes and streams? Is it a DSP engineer, a compressionist, or the producer and director? In a TV station, it's usually a combination of chief engineer and executive producer who settle what station image goes over the air. If they expend a hardware encoder, in many cases decisions about encoding parameters prize been taken out of their hands. The broadcast engineer has to labor within the parameters the chip manufacturer has allowed quit users to change, signification that while there is usually some control, there may not exist as much as a producer or engineer would like. There are only so many operations and cycles you can attach on a chip, so some functionality is uneconomical to implement.

    The Pros and Cons of Software Encoders

    General-purpose CPUs participate some similarities and architecture with dedicated processors. They are designed to exploit the everyday functions of your PC or server, and they are optimized to enact mundane tasks such as word processing. This is why your motherboard has a powerful graphics card in your machine; it's a specialty office that is best offloaded to a specific-designed processor. If you enact any nonlinear video editing, you likely prize a capture card with some specialty processors to give you real-time output or transitions.

    In the encoding and streaming industry, they mostly expend a capture board and one or more of many available software encoding packages. There are algorithms and formulas for every application, from live encoding to file-based transcoding to software-based decoding. These days most software-based encoders prize hooks in the code to offload unavoidable elements to accelerate or allow multiple CPUs to dash parallel functions to obtain the best performance and quality. More recently, Intel is offering some onboard GPUs that feature decoding with MPEG, analysis of a video stream's motion vectors, and other functions.

    GPU

    This overview shows how a GPU or video accelerator is laid out. Again, one device works as a traffic cop to transmit labor to the confiscate processors, then takes the video streams back and reassembles them together, allowing video to exist encoded at a faster rate. 

    Software encoders prize allowed users to exist much more resilient in responding to the needs of specific customers or events, and they complete expend the identical general-purpose processors and capture boards to uphold more video formats and standards. This has been an advantage for software encoders for a long time. They are easy to reconfigure and use.

    The software encoding industry has recently seen battles between open source and closed source. There are some notable pioneering closed source companies that helped drive the development of software encoding and streaming: Microsoft; existent Networks, Inc.; Sorenson Communications; and Adobe Systems, Inc. laid out the framework for modern streaming and web-based video. They prize been around since the beginning, and in many cases they financed the codecs that became standards.

    In addition to these pioneering companies, there has been a recent movement to open source. Some of the earlier versions such as x264 and the open source library in the University of California-Berkeley provide the foundation for most software encoders. Code is added every so often and allows others to program their custom apps. The better-known ones such as VideoLan (VLC), FFmpeg, and WebM are creating newfangled versions and are catching on in universal use. Some are even getting funding from some of the larger public companies. The most notable illustration is WebM, which is being funded mostly by Google, which made the VP8 codec open source after it acquired On2 Technologies. complete this competition and activity is creating better products for consumers. The huge companies realize open source development and innovation is faster-moving than their own, allowing the market to grow more quickly than it otherwise might.

    But software-based encoding has some drawbacks. The most primary parameters of encoding are quality, flexibility, price, latency, and support.

    Software encoding's greatest advantages over pure hardware encoders are its flexibility and quality. Software has always been able to adopt and update incredibly fast. When newfangled codec optimizations near out, encoding package updates succeed very soon after.

    Software encoding can enable the producer, engineer, or other user to obtain precisely the trait and image that they want, unlike the automated hardware solution, where the user has no recommend in what the overall image is and outcome will be. Some larger encoding firms hire color consultants and compressionists, along with programmers and delivery experts, complete of whom succor the executive producers and directors determine what the overall outcome should gape like. It's a broadcast approach for streaming.

    Xeon Phi

    Later this year or in early 2013, Intel will release its Xeon Phi succession of massive parallel coprocessors, which will labor with existing Xeon processors and workflows. 

    So if software encoding wins in flexibility and quality, what about quicken or latency? While some highly tuned hardware encoders present a latency down in the 30ms range, most software solutions dash in the 300ms-500ms range, if not higher. Most people who expend software encoding realize they are sacrificing some quicken for quality. complete that matters is whether or not they can obtain the resolution and framerate they want; if it's delayed some, the workflow can exist designed to accommodate it. On the other hand, if you require the lowest latency and fastest delivery, you will prize to give up some quality.

    Cost of uphold is of course an primary issue. Will the proprietary company retain making the version you're using, or is there a random it will exist withdrawn from the market? How much will the updates and upgrades cost? It turns out that upgrades in the open source community are relatively frequent, whereas upgrades in propriety software are less so.

    While some people assume that open source products present lower trait or reliability than proprietary software, that's not necessarily the case. FFmpeg, VLC, and WebM are complete significantly upping their quality. On the other hand, proprietary software packages such as Sorenson and MainConcept prize besides stood the test of time and continue to find widespread use. Interestingly, MainConcept and Sorenson are two of the few companies whose solutions are used in both software and hardware encoding; both provide codecs for the PC environment as well as specifically designed chips.

    Changes in Media Consumption, Changes in Media Encoding

    General-purpose hardware-based decoders are now playing an primary role in the overall media viewer world, especially as more and more viewers are quitting cable and going the IP route for complete of their video consumption. Roku, Boxee, and other IP set-top boxes are DSP-based decoders. At the identical time, more and more consumers are adopting Android or iOS devices and using them as personal media players, and each device brings with it its own set of pattern encoding profiles and parameters. You'll find you requisite to enact custom scaling and probably want to present the highest viable complexity. Then again, you requisite to spend more CPU cycles per frame, which will require more encoding time but create a better outcome.

    Conclusion

    There will always exist a battle between hardware encoding and software encoding. Who will win in various market segments? Why a hardware encoder versus the software encoder? Even now they are starting to note more specialty functionality appended on the general-purpose CPUs, due to the miniaturization and density of transistors and processors. For instance, Intel recently agreed to buy 190 patents and 170 patent applications from RealNetworks, and for years the company has been adding graphics processing and other accelerators or processing engines.

    Dedicated hardware encoding wins in unique parallel processing situations when massive amounts of data requisite to exist processed, as well as in low latency communications such as real-time monetary and some military applications. It besides leads in situations where you want to just install the encoding appliance and let it enact its thing, such as in situations with YouTube that can confidence on automated, predefined resolutions and bitrates for a massive amount of viewers. But software encoders will exist the appliance of altenative in most applications. It's faster and cheaper to encode with software than in hardware, and once you note how the market responds to your output, it's faster and cheaper to accomplish modifications.

    So, enact you most value flexibility and lower costs? Then software is probably your best bet. enact you requisite low latency and stream density or automated auto-transcoding for the mobile market? Then a hardware solution probably is best for you.

    This article appears in the October/November, 2012, issue of Streaming Media magazine under the title "The Specialist Vs. the Jack-of-All-Trades."

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